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1 power mosfet features ? halogen-free according to iec 61249-2- 21 definition ? dynamic dv/dt rating ? repetitive avalanche rated ? available in tape and reel ?fast switching ? ease of paralleling ? compliant to rohs directive 2002/95/ec no tes a. repetitive rating; pulse widt h li mited by maximum junction temperature (see fig. 11). b. v dd = 50 v , starting t j = 25 c, l = 37 mh, r g = 25 , i as = 1.4 a (see fig. 12). c. i sd 1.4 a , di/dt 40 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). pr oduct summ ary v ds (v ) 6 00 r ds (on) ( )v gs = 10 v 7 q g (max.) (nc) 14 q gs (nc) 2.7 q gd (nc ) 8.1 configura tion single n-channel mosfet g d s dp ak (to-252) ipak (to-251) g d s s d g d absolute maxim um ratings t c = 25 c, unless otherwise noted para meter s ymbol limit unit drain-source voltage v ds 600 v gate-source v oltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 1.4 a t c = 100 c 0.89 pulsed d rain current a i dm 5.6 linear derating factor 0.28 w/ c linear derating factor (pcb mount) e 0.020 s ingle pu lse avalanche energy b e as 93 mj re petitive aval anche current a i ar 1.4 a repetitive a valanche energy a e ar 3.6 m j maximum power diss ipation t c = 25 c p d 36 w maximum power dissipation (pc b mount) e t a = 25 c 2.5 p eak dio de recovery dv/dt c dv/dt 3.8 v /ns operating junction and s torage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 260 d * pb conta ining terminations are not rohs compliant, exemptions may apply to-220ab top v iew gds DTL1N60/dtp1n60/dtu1n60 www.din-tek.jp
2 note a. when mounted on 1" square pc b (fr-4 or g-10 material). notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. t h er mal res i sta n c e ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w maximum junction-to-ambient (pcb mount) a r thja --5 0 maximum junction-to-case (dra i n) r thjc --3 . 5 specifications t j = 25 c, unless ot herwise noted parameter symbol test co ndi tio ns min. typ. max. unit static drain-source brea kdown vo l tage v ds v gs = 0 v, i d = 250 a 600 - - v v ds temperature co efficient v ds /t j reference to 25 c, i d = 1 ma - 0.88 - v/ c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate -so urce leakage i gss v gs = 20 v - - 100 na zero g ate voltage drain current i dss v ds = 600 v, v gs = 0 v - - 100 a v ds = 480 v, v gs = 0 v, t j = 125 c - - 500 drain-sourc e on-state resistance r ds(on) v gs = 10 v i d = 1.2 a b --7.0 forw ar d transconductance g fs v ds = 50 v, i d = 1.2 a 1.4 - - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 5 - 229 - pf output capacitance c oss -42- reve rse transfer capacitance c rss -2.6- total gate charge q g v gs = 10 v i d = 1.4 a, v ds = 360 v, see fig. 6 and 13 b --14 nc gate-source char ge q gs --2.7 gate-drain charge q gd --8.1 turn-on d ela y time t d(on) v dd = 300 v, i d = 1.4 a, r g = 18 , r d = 135 , see fig. 10 b -10- ns rise time t r -13- turn-off del a y time t d(off) -30- fall tim e t f -2 5 - inte rna l dr ai n i n ductance l d between lead, 6 mm (0.25") from packag e a nd center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body di ode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integr al reverse p - n junction diode --2.0 a pulsed diode forward current a i sm --8.0 body d i ode voltage v sd t j = 25 c, i s = 1.4 a, v gs = 0 v b --1.6v body di ode reverse recovery time t rr t j = 25 c, i f = 1.4 a, di/dt = 100 a/s b - 290 580 ns body di od e reverse recovery charge q rr - 0.67 1.3 c forward t u rn-on time t on intrinsic turn-on time is negligible (tur n-o n is dominated by l s and l d ) d s g s d g DTL1N60/dtp1n60/dtu1n60 www.din-tek.jp
3 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.01 0.1 1 10 0.1 1 10 100 20s pu lse width t = 25 c j top botto m vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-sou rce vol tage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 1 10 100 20s p u lse width t = 150 c j top bott o m vgs 15v 10v 8. 0v 7.0v 6.0v 5.5v 5.0v 4.5v v , d r ain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 4.0 5.0 6.0 7.0 8.0 9.0 v = 1 0 0v 20s p uls e width ds v , gate-to-source vol t age (v) i , drain-to-source current (a) gs d t = 2 5 c j t = 150 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 0. 0 0.5 1.0 1.5 2.0 2.5 3.0 t , jun cti on temperature ( c) r , drain-to-source on resistance (normalized) j ds(o n ) v = i = gs d 10v 1.4a DTL1N60/dtp1n60/dtu1n60 www.din-tek.jp
4 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 1 10 100 1000 10000 1 10 100 1000 c, c apacitance (pf) ds v , drain-to-source voltage (v) a v = 0v, f = 1mhz c = c + c , c shorted c = c c = c + c gs iss gs gd ds rss gd o s s ds gd c iss c os s c rss 0 2 4 6 8 10 12 14 0 4 8 12 16 20 q , t o tal gate charge (nc) v , gate-to-source voltage (v) g gs fo r t est circuit see fi g ure i = d 13 1.4a v = 120v ds v = 300v ds v = 480v ds 0.1 1 10 0.4 0.6 0.8 1.0 1.2 v ,s o urce-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 0.1 1 10 100 10 100 1000 10000 op e ration in this area limited by r ds( on) si ng le pulse t t = 150 c = 25 c j c v , d ra in-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms '7/1'731'781 zzzglqwhnms
5 fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms 25 50 75 100 125 150 0.0 0.4 0.8 1.2 1.6 t , c a se temperature ( c) i , drain current (a) c d pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 not e s: 1. d u ty factor d = t / t 2. peak t = p x z + t 1 2 j dm thj c c p t t dm 1 2 t , r ectangular pulse duration (sec) therm al response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0. 5 0 sing le pu lse (t h ermal response) a r g i as 0.01 t p d.u.t l v ds + - v dd driver 15 v 20 v i as v ds t p '7/1'731'781 zzzglqwhnms
6 fi g. 12c - maximum avalanche energy vs. drain current fig. 13a - maximum avalanche energy vs. drain current fig. 12d - basic gate charge waveform fig. 13b - gate charge test circuit 25 50 75 100 125 150 0 40 80 120 160 200 st a r ting t , junction temperature ( c ) e , s ingle pulse avalanche energy (mj) j as i d to p bot t om 0. 65a 0. 9a 1. 4a q gs q gd q g v g charge v gs 670 690 710 730 750 770 0.0 0.4 0.8 1.2 1.6 a ds a v av i , avalanche current (a) v , avalanche voltage (v) d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - DTL1N60/dtp1n60/dtu1n60 www.din-tek.jp
7 fig. 14 - for n-channel p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd DTL1N60/dtp1n60/dtu1n60 www.din-tek.jp
1 to-220ab notes * m = 1.32 mm to 1.62 mm (dim ension including protrusion) heatsink hole for hvm m * 3 2 1 l l(1) d h(1) q ? p a f j(1) b(1) e(1) e e b c millimeters inches d im. min. max. min. max. a 4.25 4.65 0.167 0.183 b 0.69 1.01 0.027 0.040 b(1) 1.20 1.73 0.047 0.068 c 0.36 0.61 0.014 0.024 d 14.85 15.49 0.585 0.610 e 10.04 10.51 0.395 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 f 1.14 1.40 0.045 0.055 h(1) 6.09 6.48 0.240 0.255 j(1) 2.41 2.92 0.095 0.115 l 13.35 14.02 0.526 0.552 l(1) 3.32 3.82 0.131 0.150 ? p 3.54 3.94 0.139 0.155 q 2.60 3.00 0.102 0.118 ecn: x12-0208-rev. n, 08-oct-12 dwg: 5471 package information www.din-tek.jp
1 to-252aa (high voltage) notes 1. package body sizes exclud e mold f lash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min . ma x. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973 3dfndjh,qirupdwlrq www.din-tek.jp
1 to-251aa (high volt age) notes 1. dimensioning a nd toler ancing per asme y14.5m-1994. 2. dimension are shown in inches and millimeters. 3. dimension d and e do not include mold flash. mold flash s hall not exceed 0.13 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions b4, l2, e1 and d1. 5. lead dimension uncontrolled in l3. 6. dimension b1, b3 and c1 apply to base metal only. 7. outline conforms to jedec outline to-251aa. base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c d a c2 c lead tip 5 5 (dat u m a) thermal pad e1 4 d1 v ie w a - a a1 a a c seating plane c c b b 1 2 b 4 4 4 3 5 l1 l l3 3 x b 2 3 x b 3 b 4 e 2 x e 0.010 c b m a 0.25 0.010 b a 0.25 l2 a c m millimeters inches m illi meters inches dim. min. max. min. max. dim. min. max. min. max. a 2.18 2.39 0.086 0.094 d1 5.21 - 0.205 - a1 0.89 1.14 0.035 0.045 e 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 e1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 bsc 2.29 bsc b2 0.76 1.14 0.030 0.045 l 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 l1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 l2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 l3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 2 25' 35' 25' 35' d 5.97 6.22 0.235 0.245 ecn: s-82111-rev. a, 15-sep-08 dwg: 5968 3dfndjh,qirupdwlrq www.din-tek.jp
1 application note recommended minimum p ads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index retur n to index $ssolfdwlrq1rwh www.din-tek.jp
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